Optimal down sampling for ADC-based real-time simulation of basic power electronic converters

Abstract

In this paper, an optimal down sampler is used for Associate Discrete Circuit (ADC) based modeling and simulation of basic switching converters. Characteristic equation of backward Euler based discrete model of the circuit is used to find the value for down sampling. Using ADC modeling, fixed admittance matrix can be achieved for modeling switching converters and using down sampler, additional switch and diode current oscillations are minimized. Real-time digital simulation of buck converter using ADC with down sampler method is implemented on a Field Programmable Gate Array (FPGA) and the results are those expected without additional numerical oscillations. Based on the place-and-route results from Xilinx ISE 13.1 targeting Spartan6 XC6SLX9 FPGA, hardware in the loop are carried out, and the results are present. Experimental results show a well accordance with what expected in an offline simulation.