A bipartite, differential I/sub DDQ/ testable static RAM design

Abstract

I/sub DDQ/ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I/sub DDQ/ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I/sub DDQ/ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared.