{"title":"Low Power CMOS VCO Using an 8-shaped Transformer","authors":"Ho‐Chang Lee, S. Jang, Ren-Xiang Yang","doi":"10.1109/SiRF56960.2023.10046255","DOIUrl":null,"url":null,"abstract":"This letter designs an LC-type CMOS NP-crosscoupled voltage-controlled oscillator (VCO) using an S-shape transformer used to boost the P-FET and N-FET source voltage swings for low power dissipation. The transformer uses two 3-turn coils twisted in series as the primary and the layout method reduces the number of crossing metal lines and parasitic capacitance. The one-turn 8-shaped secondary interleaves with the primary to get high-coupling coefficient. The transformer topology enables symmetric transformer layout and the two lobes of the 8-shaped primary and secondary inductors radiate far-field magnetic fields to suppress the magnetic field radiation. The die area of the VCO in the TSMC 0.1S$\\mu$m CMOS process is 0.762 × 0.S55 mm2. The measured phase noise of the VCO at 2. 7S GHz.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"80 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiRF56960.2023.10046255","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This letter designs an LC-type CMOS NP-crosscoupled voltage-controlled oscillator (VCO) using an S-shape transformer used to boost the P-FET and N-FET source voltage swings for low power dissipation. The transformer uses two 3-turn coils twisted in series as the primary and the layout method reduces the number of crossing metal lines and parasitic capacitance. The one-turn 8-shaped secondary interleaves with the primary to get high-coupling coefficient. The transformer topology enables symmetric transformer layout and the two lobes of the 8-shaped primary and secondary inductors radiate far-field magnetic fields to suppress the magnetic field radiation. The die area of the VCO in the TSMC 0.1S$\mu$m CMOS process is 0.762 × 0.S55 mm2. The measured phase noise of the VCO at 2. 7S GHz.