Using SAT techniques in dynamic burn-in vector generation

Abstract

Dynamic burn-in testing is an integral component of any test plan that seeks to produce reliable integrated circuits. Despite its importance in ensuring the reliability of semiconductors, burn-in has been a major contributor to overall test cost and turnaround time. In this work we discuss the application of advanced Boolean satisfiability (SAT) techniques to generate a set of vectors or input stimuli that increases the nodal activity in the circuit and hence the elevation of its temperature. The vectors are designed to uniformly stress all parts of the circuit. Additionally, we present a SAT-based methodology where weak nodes can selectively be targeted for high switching activity in an effort to detect potential failures. Finally, SAT-based solvers are compared against generic Integer Linear Programming (ILP) solvers when handling the vector generation problem.