J. Rettkowski, Safdar Mahmood, Arij Shallufa, M. Hübner, D. Göhringer
{"title":"Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks","authors":"J. Rettkowski, Safdar Mahmood, Arij Shallufa, M. Hübner, D. Göhringer","doi":"10.1109/IPDPSW.2019.00023","DOIUrl":null,"url":null,"abstract":"Incorporating FPGAs in embedded designs, both for research and industry related applications, is getting increasingly common. Due to the inherent capability of an FPGA to reconfigure itself during run-time, entirely or partially, it has become a very cost effective and time efficient solution for end-users with ever-changing needs for their embedded and custom hardware designs. This capability allowing dynamic reconfiguration of FPGAs, unfortunately also poses a threat to hardware security in terms of malicious bitstream manipulation that can include attacks through intended hardware changes by insertion of hardware trojans, spy-wares or even energy thirsty hardware modules which eventually have adverse effects on energy critical applications. In this paper, we introduce a novel approach to tackle this problem using machine learning techniques for FPGA bitstream analysis. By making use of different Neural Networks, we present how it paves a way to analyze partial FPGA bistreams to trace a certain module, or to find inconsistencies which can be malicious to the target hardware. In contrast to traditional methods to inspect bitstreams, our method saves a significant amount of time.","PeriodicalId":292054,"journal":{"name":"2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPDPSW.2019.00023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Incorporating FPGAs in embedded designs, both for research and industry related applications, is getting increasingly common. Due to the inherent capability of an FPGA to reconfigure itself during run-time, entirely or partially, it has become a very cost effective and time efficient solution for end-users with ever-changing needs for their embedded and custom hardware designs. This capability allowing dynamic reconfiguration of FPGAs, unfortunately also poses a threat to hardware security in terms of malicious bitstream manipulation that can include attacks through intended hardware changes by insertion of hardware trojans, spy-wares or even energy thirsty hardware modules which eventually have adverse effects on energy critical applications. In this paper, we introduce a novel approach to tackle this problem using machine learning techniques for FPGA bitstream analysis. By making use of different Neural Networks, we present how it paves a way to analyze partial FPGA bistreams to trace a certain module, or to find inconsistencies which can be malicious to the target hardware. In contrast to traditional methods to inspect bitstreams, our method saves a significant amount of time.