A low-power Clock and Data Recovery circuit for 2.5 Gb/s SDH receivers

Abstract

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f/sub T/ silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2/sup 23/-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.