Study on a $0.13-\upmu \mathrm{m}$ CMOS Class-E 2.4 GHz Adjustable Power Amplifier for IoT Application

Abstract

Power amplifier (PA) is one of the most power-consuming blocks in a transmitter. It is critical to improve power-added efficiency (PAE) in the design of a PA. This paper presents a 2.4 GHz class-E PA particularly designed with a two-stage architecture. The inverter driver stage outputs a full swing square wave to control the on-off of the power stage. By using cascode self-biased topology in the power stage, the peak drain-gate voltage is reduced and the problem caused by transistor breakdown voltage can be overcome. According to the post-simulated results, the proposed PA provides greater than 35% PAE while delivering adjustable saturation output power (Psat) between 9.3 and 17.6 dBm at the center frequency of 2.4 GHz in $0.13 \mu \mathrm{m}$ CMOS. In the maximum Psat state, the PAE is 40.6% with a 1.2V supply voltage and the optimum load resistance obtained in load-pull simulation.