A prototype analog/mixed-signal fast fourier transform processor IC for OFDM receivers

Abstract

A prototype FFT processor IC that reduces linearity requirements of analog-to-digital converters in broadband orthogonal-frequency-division-multiplexing (OFDM) receivers is presented. The processor is based on a time-interleaving bank of sample-and-holds and a discrete- time analog multiplication based FFT. The circuit design of the prototype IC is presented and measurement results from the 0.13 mum test chip are shown. The FFT length-8 prototype successfully demodulates a complex OFDM signal at 1 GSps while drawing 25 milliwatts of power from a 1.2 Volt supply and achieving an error vector magnitude of 2.8%.