Hardware Accelerator for Edge Detection

Abstract

Hardware accelerators have been recently proposed for computationally extensive applications like real-time video image processing systems. Contemporary hardware accelerators are implemented by using either Field Programmable Gate Array (FPGA) or System-on-Chip (SoC) devices. Edge detection is a fundamental task for any image processing system. In this paper, a pipelined architecture for a fuzzy logic edge detection system is proposed. The system has been implemented and tested on various Xilinx 7 Series devices. The hardware accelerator core utilizes a pipeline of seven stages. Depending on the available resources the accelerator system can be made up of several cores operating simultaneously. A single-core implementation of the system can process a 1080P HD test frame at a rate of about 45 frames per second. It outperforms its software counterpart by a factor of ten thousand.