A high-speed vision processor based on pixel-parallel PE array and its applications

Cong Shi, N. Wu, Zhihua Wang
{"title":"A high-speed vision processor based on pixel-parallel PE array and its applications","authors":"Cong Shi, N. Wu, Zhihua Wang","doi":"10.1109/YCICT.2010.5713151","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel high-speed vision processor based on pixel-parallel PE array. The processor consists of a pixel-parallel PE array, an embedded RISC core, an AHB bus, some SRAM blocks and other logical controllers. PE array performs the low- and mid-level vision processing, and RISC core carries out the high-level vision processing in succession. The vision processor can process vision information at a speed higher than 1000fps. Many application algorithms can be implemented by software programming on the vision processor. The processor prototype is implemented on a FPGA board with a 64×64 PE array and the clock frequency is 100MHz. It can realize moving detection in 128×128 image data at a rate of 4500fps, and 104fps in complicated face detection task for 160×120 video frame sequence. The results demonstrated that the vision processor outperforms the general serial CPUs for more than 60 times.","PeriodicalId":179847,"journal":{"name":"2010 IEEE Youth Conference on Information, Computing and Telecommunications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Youth Conference on Information, Computing and Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/YCICT.2010.5713151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper proposes a novel high-speed vision processor based on pixel-parallel PE array. The processor consists of a pixel-parallel PE array, an embedded RISC core, an AHB bus, some SRAM blocks and other logical controllers. PE array performs the low- and mid-level vision processing, and RISC core carries out the high-level vision processing in succession. The vision processor can process vision information at a speed higher than 1000fps. Many application algorithms can be implemented by software programming on the vision processor. The processor prototype is implemented on a FPGA board with a 64×64 PE array and the clock frequency is 100MHz. It can realize moving detection in 128×128 image data at a rate of 4500fps, and 104fps in complicated face detection task for 160×120 video frame sequence. The results demonstrated that the vision processor outperforms the general serial CPUs for more than 60 times.
基于像素并行PE阵列的高速视觉处理器及其应用
提出了一种基于像素并行PE阵列的高速视觉处理器。该处理器由像素并行PE阵列、嵌入式RISC核心、AHB总线、一些SRAM块和其他逻辑控制器组成。PE阵列进行低级和中级视觉处理,RISC内核依次进行高级视觉处理。视觉处理器可以以高于1000fps的速度处理视觉信息。许多应用算法都可以在视觉处理器上通过软件编程实现。该处理器原型采用64×64 PE阵列在FPGA板上实现,时钟频率为100MHz。它能以4500fps的速度对128×128图像数据进行运动检测,对160×120视频帧序列进行104fps的复杂人脸检测。结果表明,该视觉处理器的性能优于普通串行cpu 60倍以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信