A multi-level approach to low power MAC design

Abstract

A low power 8/spl times/8+20-bit MAC is designed minimizing the power consumption at each of the design levels. At algorithm level, a new method for MR-XY operation which saves 40% of transistor counts over conventional methods is proposed. A new Booth selector circuit using NMOS PTL (pass-transistor logic) which has excellent power-delay product is also proposed at transistor level. Dynamic CMOS single edge triggered flip-flops are used to reduce the number of transistors for the registers. The proposed MAC is designed with 0.6 um single-poly triple-metal CMOS process. As a result of simulation, operating frequency is over 100 MHz with 3.3 V supply voltage and the average power consumption is 51 mW at 100 MHz.