Accelerating multiple alignment on FPGA with a high-level hardware description language

Abstract

The paper describes an experience of creating a hardware implementation of a pairwise sequence alignment algorithm in a high-level hardware description language. The implementation is created to be run on an FPGA with a high latency interface to a PC (ethernet). Thus, a lot of control logic is implemented in hardware together with the main pipeline. We use a HaSCoL hardware description language for that purpose and discuss pros and cons of this approach compared to software implementation of the control logic on an embedded processor. We also discuss how the language helps to describe hardware and how it could help more as well.