Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters

Abstract

Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.