Energy Efficient ADC for Low Fan-Out MIMO Sub- THz Imaging System in SiGe: BiCMOS Technology

Abstract

This paper presents a top-down architectural analysis of a MIMO imaging system in terms of analog-to-digital converter (ADC) requirements. This helps to determine the optimal ADC accuracy and make the right choice for an ADC circuit architecture, without going into an over design effort. It results in a 32 MS/s 8-bit SAR ADC based on a hybrid DAC architecture. The ADC was designed in a 130nm SiGe BiCMOS process, demonstrating core power consumption of 0.3mW from a 1.2V supply. The ADC core occupies a 0.23×0.13mm2 silicon area and can be easily integrated with a 220–260 GHz imaging receiver on the same IC. It will significantly improve power consumption, form factor and assembly of the complete MIMO imaging system.