Five Stage Pipelined MIPS Processor Verification Scoreboard Module using UVM

Abstract

In the VLSI design flow, functional verification is an essential step that is necessary to identify bugs in the hardware description. The complexity and size of digital designs have increased significantly, making functional verification mandatory. Surveys have shown that verification takes up to 70% of the total project time, whereas the design phase requires only 30%. Therefore, it is crucial to develop an efficient verification framework to avoid time-to-market delays. This research paper focuses on the development of a simulation-based verification platform for the RISC-V processor. The study describes the design of as-stage pipelined MIPS processor using UVM, supporting a 32-bit instruction set. The different modules involved in the design include Data Memory, Registers, Instruction Memory, and ALU. Additionally, a hazard detection and forwarding unit has been implemented to automate the detection of data hazards during verification.