L. Clark, V. Vashishtha, D. Harris, Samuel Dietrich, Zunyan Wang
{"title":"Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit","authors":"L. Clark, V. Vashishtha, D. Harris, Samuel Dietrich, Zunyan Wang","doi":"10.1109/MSE.2017.7945071","DOIUrl":null,"url":null,"abstract":"Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.","PeriodicalId":339888,"journal":{"name":"2017 IEEE International Conference on Microelectronic Systems Education (MSE)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Conference on Microelectronic Systems Education (MSE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSE.2017.7945071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27
Abstract
Educators and researchers exploring integrated circuit design methods need models and design flows for advanced integrated circuit processes. As commercial processes have become highly proprietary, predictive technology models fill the gap. This work describes a design flow for ASAP7, the first 7 nm FinFET PDK, including schematic and layout entry, library characterization, synthesis, placement and routing, parasitic extraction, and HSPICE simulation.