{"title":"Delay-sum beamforming on FPGA","authors":"Peng Chen, Xiang Tian, Yao-wu Chen, Xiaofan Yang","doi":"10.1109/ICOSP.2008.4697667","DOIUrl":null,"url":null,"abstract":"This paper presents one multi-FPGA system board for implementing delay-sum beamforming of three-dimensional (3-D) sonar in the frequency-domain. The Matlab simulation is demonstrated by splitting the delay-sum beamforming into two steps where two stages FPGAs system implementation is utilized. This paper also analyzes discrete Fourier transform (DFT) of sample data, the communication bandwidth and memory requirements of this system architecture. The paper illustrates that the proposed multi-FPGA system can implement 10,000 beams and 576 sensors of 2 KHz beamspsila array update rate per second. The performance advantage is supported by the rapid development of serial communication and the configurable high performance FPGAs.","PeriodicalId":445699,"journal":{"name":"2008 9th International Conference on Signal Processing","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICOSP.2008.4697667","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents one multi-FPGA system board for implementing delay-sum beamforming of three-dimensional (3-D) sonar in the frequency-domain. The Matlab simulation is demonstrated by splitting the delay-sum beamforming into two steps where two stages FPGAs system implementation is utilized. This paper also analyzes discrete Fourier transform (DFT) of sample data, the communication bandwidth and memory requirements of this system architecture. The paper illustrates that the proposed multi-FPGA system can implement 10,000 beams and 576 sensors of 2 KHz beamspsila array update rate per second. The performance advantage is supported by the rapid development of serial communication and the configurable high performance FPGAs.