{"title":"High voltage DMOS power FETs on thin SOI substrates","authors":"J. O'connor, V. Luciani, A. Caviglia","doi":"10.1109/SOSSOI.1990.145765","DOIUrl":null,"url":null,"abstract":"A 90 V, 1.3 A double-diffused MOS (DMOS) power FET fabricated on a 400 nm thick SOI (silicon-on-insulator) film is reported. By utilizing thin SOI materials, these devices can be easily integrated with analog and digital devices to form smart power monolithic circuits. The power devices can be isolated from each other and from the control circuitry by either etching or oxidizing (local oxidation of silicon) through the thin SOI layer, and both high and low side drivers can be combined on a single chip. The thin SOI layer virtually eliminates step coverage problems with interconnects and avoids complicated planarization schemes often needed for dielectrically isolated power devices.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 IEEE SOS/SOI Technology Conference. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOSSOI.1990.145765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A 90 V, 1.3 A double-diffused MOS (DMOS) power FET fabricated on a 400 nm thick SOI (silicon-on-insulator) film is reported. By utilizing thin SOI materials, these devices can be easily integrated with analog and digital devices to form smart power monolithic circuits. The power devices can be isolated from each other and from the control circuitry by either etching or oxidizing (local oxidation of silicon) through the thin SOI layer, and both high and low side drivers can be combined on a single chip. The thin SOI layer virtually eliminates step coverage problems with interconnects and avoids complicated planarization schemes often needed for dielectrically isolated power devices.<>