Compiling VHDL into a high-level synthesis design representation

Abstract

An approach to the use of VHDL (VHSIC hardware description language) as an input specification to the CAMAD high-level synthesis system is presented. A synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the interal design representation of CAMAD is described. CAMAD can then be synthesized into register-transfer level design. Since CAMAD supports the design of hardware with concurrency and asynchrony, the VHDL subset includes the concurrent features of the language. Conclusions concerning how to deal with signals, wait statements, structured data, and subprograms are presented.<>