A Case of Chip Multithreading Architecture with Resource Unit Manager

Abstract

In order to improve the overall throughput of processors, to increase thread-level parallelism (TLP) and instruction-level parallelism (ILP) intra and inter cores, and ensure the scalability of multi-core systems, can a novel mechanism chip multithreading with resource unit manager (RUM-CMT) be used, which is presented in this paper. By introducing the efficiency difference of resource utilization among threads, such as, the condition of dynamically resource allocation to CMT architecture and add an absorption barrier for all threads to make their reserved resources far away from hidden hunger. For verify the applicability of RUM-CMT, a 4 cores with 2 threads processor and a 4 cores with 4 threads processor are simulated based on GEMS & Simics simulator. And this limited study shows RUM-CMT can increase performance by 29.79%, and an improve success committed instructions per squash instructions by 31.15% and fairness attains 6.25% improvements over static partition on 4 cores with 4 threads processor. The 4 cores with 2 threads also attains passable enhance. So RUM-CMT can accurately and concise reallocate resource according to phase turning in the running of applications, improve resource utilization, mining the ILP and TLP in applications. In other words, RUM-CMT improves the controllability of threads, reduces invalid losses and improves system efficiency, and it is a suitable solution for multicore, multithreaded architecture.