An Algorithm for Reducing Leakage Power Based on Dual-Threshold Voltage Technique

Abstract

To reduce the static power of the circuit, a dual-threshold voltage assignment algorithm has been proposed in this paper. This algorithm uses static timing analysis to get the timing information of all nodes by double traverse and assigns the threshold voltage of each node through initial optimization and accurate optimization. Under given timing constraint, the goal of our algorithm is to replace a maximum number of high-Vt gates from low-Vt in the circuit and maximize the reduction of the static power. Our dual-threshold voltage assignment algorithm and traditional method are compared based on the embedded CPU CK610 of TSMC 55nm process. The results show that our algorithm can reduce the static power of the chip by 60.07%.