An automated SAT-based method for the design of on-chip bit-flip detectors

Abstract

Hardware invariants are known to facilitate bit-flip detection during post-silicon validation. In this paper, we present a fully automated SAT-based methodology for fast generation of hardware invariants by using the built-in pruning mechanisms within SAT solvers, namely learned clauses. These candidates are evaluated for their potential to detect bit-flips using a new incremental SAT-based approach. In addition to speeding-up the simulation-based approaches for invariant generation and evaluation, when compared to the known art, our results show improvements in both the number of flip-flops that can be covered for bit-flip detection, as well as for the on-chip area for the bit-flip detection unit.