{"title":"The design of a bus controller based on SOC in industrial control system","authors":"Ma Yan, Wang De-li","doi":"10.1109/ICCDA.2010.5540786","DOIUrl":null,"url":null,"abstract":"Based on the analysis of PC104 bus protocol, a design of synchronous PC104 bus controller is proposed in a SOC(System-on-Chip). With the demands of quick interrupt response time, low power and high reliability for the application of aviation and the characteristic of SOC, lots of efforts are made on the these targets. These techniques mainly include internal module data path optimization, internal module bus cycle speed-up. Some key signals are processed by noise-reduced scheme. Over-delay logic is added for recovery from possible halt state. Experiments show that the operating system booting time has been reduced by 7.3%, and the energy consumed is reduced by 17.1% corresponding. A SOC integrating this controller has been manufactured and the real system is quite reliable and the interrupt response time is reduced by 14%.","PeriodicalId":190625,"journal":{"name":"2010 International Conference On Computer Design and Applications","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference On Computer Design and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDA.2010.5540786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Based on the analysis of PC104 bus protocol, a design of synchronous PC104 bus controller is proposed in a SOC(System-on-Chip). With the demands of quick interrupt response time, low power and high reliability for the application of aviation and the characteristic of SOC, lots of efforts are made on the these targets. These techniques mainly include internal module data path optimization, internal module bus cycle speed-up. Some key signals are processed by noise-reduced scheme. Over-delay logic is added for recovery from possible halt state. Experiments show that the operating system booting time has been reduced by 7.3%, and the energy consumed is reduced by 17.1% corresponding. A SOC integrating this controller has been manufactured and the real system is quite reliable and the interrupt response time is reduced by 14%.