On topology and bisection bandwidth of hierarchical-ring networks for shared-memory multiprocessors

Abstract

Hierarchical-ring based multiprocessors are interesting alternatives to the more popular two-dimensional direct networks. They allow for simple router designs and wider communication paths than their direct network counterparts. There are several ways hierarchical-ring networks can be configured for a given number of processors. Feasible topologies range from tall, lean networks to short, wide networks, but only a few of these possess high throughput and low latency. We present the results of a simulation study: to determine how large hierarchical-ring networks can become before their performance deteriorates due to their bisection bandwidth constraints; and to derive topologies with high throughput and low latency for a given number of processors. We show that a system with a maximum of 120 processors and three levels of hierarchy can sustain most memory access behaviours, but that larger systems can be sustained, only if their bisection bandwidth is increased.