Challenges for analog circuits in sub-100 nm CMOS nodes

Abstract

New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example, the matching behavior of long channel and short channel halo-doped MOSFETS is examined. Furthermore, the disadvantages of the BEOL (Back End Of Line) due to the smaller dimensions are analyzed. Especially the reliability requirements of these BEOL design rules are discussed. Consequences on the layout are demonstrated by applying an EM & IR drop tool.