Dynamic task mapping of graphics processing applications on many-core architectures through stream rewriting

Abstract

Although modern graphics processing units (GPU) contain a large number of programmable shader cores, the focus on data parallelism and also the lack of efficient on-chip communication hinder the creation of custom graphics pipelines with arbitrary topologies. Based on the concept of stream rewriting, we propose a novel many-core architecture for graphics processing, which supports dynamic scheduling of recursively expandable task graphs and graphics pipelines. In particular, the tasks and their dependencies are encoded as a token stream, which is iteratively rewritten via pattern matching on multiple cores in parallel. The scalability of the proposed hardware architecture has been evaluated using an FPGA prototype.