In-line testing of blind TSVs for 3D IC integration and M/NEMS packaging

Abstract

An in-line testing procedure of blind TSVs is put forward in this study. Insulation integrity is chosen to determine the eligibility. It is to probe the upper end of two or more neighboring TSVs during the manufacturing right after the blind vias being formed. Finite element method simulation was used to illustrate the testing principle, and experimental test were carried out for validation. During the test, leakage current data between two blind vias is obtained and I-V characteristic curve is plotted. It can be determined whether or not the TSVs are qualified.