An 11 bit SAR ADC combining a split capacitor array with a resistive ladder and a configurable noise time domain comparator

Abstract

This paper presents a successive approximation analog to digital converter with a configurable resolution of 8 or 11 bit. The resolutions are achieved by combining an 8 bit split capacitor array with a 3 bit resistive ladder allowing for a simpler layout and good power efficiency. Configurable buffers are included and enable a wide range of operation frequencies. Sample rates between 300S/s and 80kS/s were tested where at the lower frequency a total current consumption of just 8.4nA was measured. A configurable time domain comparator is employed to adapt the noise requirement to the desired resolution. The circuit is developed in a 130nm CMOS technology and occupies an active area of 0.0664mm2.