Highly fault-tolerant FPGA processor by degrading strategy

Abstract

The importance of highly fault-tolerant computing systems has widely been recognized. We propose an FPGA architecture with a degrading strategy to increase fault-tolerance in a CPU. Previously, duplication and substitution methods have been proposed, but former methods waste redundant circuits and later methods increase computing speed as faults occur. We propose a reconstitution method with FPGA technology. Using our method, execution speed of the CPU gradually decreases as permanent faults occur. The CPU consists of functional blocks (FB), that is re-configurable logic blocks. When a fault occurs, the broken FB is discarded. As the number of valid FB decreases, function units of it is scaled down, therefore, execution time increases. In our simulation, speed degradation is less than 100% when 70% of whole FBs are broken. Compared with previous methods, speed degradation is smaller in case that many permanent faults occur.