Optimal Virtual Channel Insertion for Contention Alleviation and Deadlock Avoidance in Custom NoCs

Abstract

Deadlock and contention can be avoided in an NoC architecture by employing virtual channels (VC). VC insertion can result in power and chip area increases with little performance improvements. We present a novel VC insertion technique for deadlock avoidance and contention relief in irregular NoC architectures that avoids significant power and area increase. Given a resource pool of VCs, deadlock/contention analytical models, and a systematic pre-evaluation technique, minimal VC resources are inserted resulting in higher performance. Several experiments are conducted on various SoC benchmark applications. The results of our technique indicate an average performance improvement of 21%, 32.4% decrease in power dissipation and 79.5% resource savings as compared to past techniques.