A new transistor of dual-gate SOI and evidence for diminished short channel effects

Abstract

In this paper a new transistor of dual-gate (DG) silicon-on- insulator (SOI) MOSFET is presented. The objects of this paper are to use a voltage difference between the two gates to screen the drain voltage and therefore reduce short channel effects (SCEs). In this transistor the surface potential exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and decreasing off-current with respect to shrinking of channel length. The obtained results of our transistor are compared to single gate (SG) SOI MOSFET that shows the DG SOI MOSFET performance is superior. The transistor has been simulated by SILVACO software.