{"title":"Extensible processor speeds up IP lookup","authors":"P. Gautam, M. Jagtap","doi":"10.1109/ICON.2012.6506593","DOIUrl":null,"url":null,"abstract":"With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack programmability, scalability and flexibility. Upgradation of services and protocols necessitates programmability of routers. In this paper, we present a cost effective and flexible solution to achieve fast IP lookup using extensible and configurable processor. Configurable and extensible processor can be tuned by the designer to accelerate applications by selecting suitable processor parameters, adding new instructions and hardware. We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz.","PeriodicalId":234594,"journal":{"name":"2012 18th IEEE International Conference on Networks (ICON)","volume":"92 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 18th IEEE International Conference on Networks (ICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICON.2012.6506593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
With ever increasing internet link speeds and growing routing table size, IP address lookup has been major performance bottleneck for routers. Traditionally ASIC or CAM based solutions are used to achieve the demanding performance requirements of IP lookup. These solutions are costly as well as lack programmability, scalability and flexibility. Upgradation of services and protocols necessitates programmability of routers. In this paper, we present a cost effective and flexible solution to achieve fast IP lookup using extensible and configurable processor. Configurable and extensible processor can be tuned by the designer to accelerate applications by selecting suitable processor parameters, adding new instructions and hardware. We have used Eatherton Tree Bitmap algorithms for address lookup and developed instructions that are optimized to yield large performance improvements. With the addition of these newly created instructions, a lookup performance of 17.5 Million lookups per second (Mlps) is achieved for processor running at 500 Mhz.