Technology driven High-Level Synthesis

Abstract

present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Syn- thesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. Keywords: High-Level Synthesis, Target Technology, At- tribute Grammars, Optimization, FPGA.