Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter

Abstract

A digital phase-locked loop (DPLL) consists of a time-to-digital converter (TDC) or phase detector (PD), a digital loop filter (DLF), an oscillator, and a divider. DPLL has several advantages over traditional analog charge-pump (CP) PLL. It is resistant to process, voltage, and temperature (PVT) variations and has a large voltage and frequency synthesis range. To achieve the desired bandwidth, CPPLLs require large capacitance that occupies a significant silicon area. In comparison, DPLL can reduce the size of the filter capacitor. The synthesized frequency or phase of the DPLL is adjusted both with the proportional and integral path inside the DLF. It is difficult to adjust the frequency all at once with a large proportional gain. And if the delay is formed in the entire loop of the PLL, there is a problem in that the stability of the loop is reduced. An improved DPLL model to overcome the aforementioned defects is proposed and validated in this manuscript.