F. Vanselow, Prajith Kumar Poongodan, Oleg Sakolski, L. Maurer
{"title":"A New Switching Scheme For High-Voltage Switched Capacitor DC-DC Converter","authors":"F. Vanselow, Prajith Kumar Poongodan, Oleg Sakolski, L. Maurer","doi":"10.1109/MOCAST52088.2021.9493344","DOIUrl":null,"url":null,"abstract":"In this paper a new double switch bootstrapping (DSB) scheme for high voltage switched capacitor DC-DC converter is presented. The circuit enables charge pump input voltages greater than the gate-oxide breakdown voltage for the switches. The DSB scheme is implemented in two high-voltage linear charge-pumps for positive and negative output voltages of up 72V and down to -36V, a maximum input voltage of 9V, a load current of 300µA for an efficiency of 34.8% at 2.2 MHz switching frequency. The experimental testchip is realized using a high-voltage 0.18µm SOI technology in 6.54 mm2.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST52088.2021.9493344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper a new double switch bootstrapping (DSB) scheme for high voltage switched capacitor DC-DC converter is presented. The circuit enables charge pump input voltages greater than the gate-oxide breakdown voltage for the switches. The DSB scheme is implemented in two high-voltage linear charge-pumps for positive and negative output voltages of up 72V and down to -36V, a maximum input voltage of 9V, a load current of 300µA for an efficiency of 34.8% at 2.2 MHz switching frequency. The experimental testchip is realized using a high-voltage 0.18µm SOI technology in 6.54 mm2.