OS-level Implications of Using DRAM Caches in Memory Disaggregation

Abstract

Memory disaggregation has attracted great attention recently due to its benefits in resource utilization efficiency, isolation of failures, and easier reconfiguration of memory hardware. However, applications running on a system with disaggregated memory are expected to suffer from performance degradation due to increased remote memory access latency and network contention. The performance gap is meant to be bridged using DRAM caches on the processor side, which would filter out most of the network traffic.This work examines the overheads of the disaggregated memory abstraction. By experimenting with both micro-benchmarks and production applications, we observe severe degradation in memory access latency and potential bottlenecks within the OS kernel. These bottlenecks could potentially be avoided through low-level optimizations in memory management tailored for memory disaggregation.