A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing

Abstract

This paper addresses the issue of blocking pattern selection to reduce both leakage and peak power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to circuit inputs. This though reduces dynamic power significantly, can result in quite an increase in the leakage power and peak power. We have presented a novel approach to select a blocking pattern that reduces both peak and leakage power. The avg. improvement in peak power is 31.8% and that of leakage power is 13.5% (best is around 51.2% & 24.9% respectively) with respect to all 1's vector.