Design and Application of a Novel 4-Transistor Chaotic Map with Robust Performance

Abstract

A new one dimensional discrete chaotic map circuit is presented. The design is done in a 45 nm CMOS process but the proposed topology is generally applicable for any technology node. The design is hardware-efficient as it contains only four MOS transistors and offers robust chaotic performance with a wide chaotic range. The chaotic performance is analyzed using bifurcation plot, Lyapunov exponent, correlation coefficient, and sample entropy. These different qualitative and quantitative measures clearly demonstrate excellent ergodic properties across a wide chaotic parameter range. The proposed map is also used in designing a reconfigurable logic generator and its wide chaotic window is shown to significantly enhance the functionality space of the logic generator.