A new modeling method for vector processor pipeline using queueing network

Abstract

Embedded vector processor is a kind of high-performance parallel processor. Pipeline design is a key technology in embedded vector microprocessors. This paper proposes a new modeling method for vector processor pipeline using open queueing network by instruction set feature of vector processor. According to instruction set distribution of vector processor in the practical projects and owing in the pipeline modeling, the model of pipeline queueing network is analyzed. Total delay and mean delay are computed in every path. A better solution of pipeline is put forward as a result of delay data. Serving time of server nodes is averaged by partitioning for pipeline modeling and adding processing nodes in executing model. In conclusion, the delay data before and after improvement pipeline scheme are analyzed: the delay distributing of improvement scheme is almost equality and choke points with long delay and unequal are avoided.