Design and implementation of 16 bit systolic multiplier using modular shifting algorithm

Abstract

The finite field multipliers consuming high-throughput rate and low-latency having grown excessive attention in recent cryptographic systems, and coding theory but such multipliers above Galois field GF(2m) for National institute standard technology (NIST) pentanomials are not so plentiful. We introduce two pairs of low latency and high throughput bit-parallel and digit-serial systolic multipliers depends on NIST pentanomials. We propose a unique decomposition technique to recognize the multiplication by several parallel arrays in a two-dimensional (2-D) systolic structure (BP-I) with a critical-path of 2Tx, where Tx is the propagation delay of XOR gate. The parallel arrays in two dimensional systolic structure are estimated along the vertical direction to attain a proposed 16-bit digit-serial structure (PDS-I) with the same critical-path. Designed for high-throughput applications, we proposed another pair of bit-parallel (BP-II) and Modified 16 bit digit-serial (PDS-II) structures based on a unique modular reduction method, where the critical-path is reduced to(Ta+Tx), Ta is an propagation delay of AND gate. The steps for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been suggested to reduce the area-complexity of BP-I and BP-II advance. The existing method consumes more power and high area overhead. In systolic multiplier used to reduce area and power for the ASIC implementations and is also reduce the average computation time. Systolic multiplier is a better choice for high-speed VLSI implementation.