Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic

Abstract

Conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry, and converts them considering reduction of the number of clocked gates. It utilizes two characteristics of pulse logic for the reduction. One is utilizing confluence of pulses to realize logic-OR. The other is utilizing a small resettable DFF as an NIMPLY gate by tuning the order of pulse arrival. To minimize the number of clocked gates with minimum replacements of gates, the selection problem of gates for replacements utilizing those characteristics and assignment of logic level to each gate are formulated as an instance of integer linear programming.