A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter

Abstract

A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.