{"title":"Exploiting fine-grained parallelism through a combination of hardware and software techniques","authors":"S. Melvin, Y. Patt","doi":"10.1145/115953.115981","DOIUrl":null,"url":null,"abstract":"It has been suggested that non-scientific code has very little parallelism not already exploited by existing vrocesso~s. In this ABSTRACT It has been suggested that non-scientific code has very little parallelism not already exploited by existing vrocesso~s. In this paper we show that &nt& to this notiOK (here is actually a significant amount of unexploited parallelism in typical general purpose code. In order to exploit this parallelism, a combination of hardware and software techniques must be applied. We analyze three techniques: dynamic scheduling, speculative execution and basic block enlargement. We will show that indeed for narrow instruction words little is tobegainedby applying these techniques. However, as the number of simultaneous operations increases, it becomes possible to achieve speedups of three to six on realistic processors.","PeriodicalId":187095,"journal":{"name":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/115953.115981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 49
Abstract
It has been suggested that non-scientific code has very little parallelism not already exploited by existing vrocesso~s. In this ABSTRACT It has been suggested that non-scientific code has very little parallelism not already exploited by existing vrocesso~s. In this paper we show that &nt& to this notiOK (here is actually a significant amount of unexploited parallelism in typical general purpose code. In order to exploit this parallelism, a combination of hardware and software techniques must be applied. We analyze three techniques: dynamic scheduling, speculative execution and basic block enlargement. We will show that indeed for narrow instruction words little is tobegainedby applying these techniques. However, as the number of simultaneous operations increases, it becomes possible to achieve speedups of three to six on realistic processors.