Reliability-aware register binding for control-flow intensive designs

Abstract

As soft error is a major reliability issue for nanoscale VLSI, addressing it during high level synthesis can have a significant impact on the overall design quality. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables have nonuniform soft error vulnerabilities, we propose a novel reliability-aware register binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive variable vulnerability analysis at the behavioral level, by considering error propagation and masking in both control and data flow. Then an optimization based on integer linear programming is used to incorporate vulnerabilities into the register binding phase with a selective register protection scheme. The experimental results reveal that the proposed technique can achieve significant soft error mitigation (60% coverage of the total vulnerabilities) with a small portion (20%) of register protection.