{"title":"Digital Signal Generator and Receiver design For S-band Radar","authors":"L. Prakasam, T. Roy, D. Meena","doi":"10.1109/RADAR.2007.374405","DOIUrl":null,"url":null,"abstract":"The new generation of radar has to be equipped with a high performance exciters and receivers to cope with the threat in an Electronic Warfare scenario. The threat in a complex environment with interfering signals requires a reliable signal generation with proper frequency agility and efficient gain controls in receiver units. This is quite cumbersome to achieve in analog domain. Due to digital technology advancements, it is possible to have efficient and high performance Analog-to-Digital converters (ADC),processors, high-density memories and efficient algorithms to realize highly reliable, flexible and upgradeable exciters and receivers. In this design, exciter unit comprises of various digital modules for waveform generation, clocks and synchronization signal generation for different sub-systems of the radar and digital code generation for the frequency to be synthesized. These codes are used to control the Local Oscillators (LOs) output utilized for the up-conversion. In the Receiver unit main focus is on the digital implementation of gain control like sensitivity-time-control (STC), Generation of various controls required by Synthetic noise generator and Automatic Gain Control (AGC) and Digital amplitude Phase Demodulation (DAPD) of down-converted sampled intermediate frequency (IF) signals. This work projects the digital design methodology behind the various modules identified for the Radar Signal Generation and Receiver units. The main highlight of the paper is that the entire design models described are implemented using digital methods using FPGAs. The Xilinx System Generator (XSG) design tool is used to accomplish this, which generates directly the code for a Xilinx FPGA on a target board.","PeriodicalId":367078,"journal":{"name":"2007 IEEE Radar Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Radar Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADAR.2007.374405","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
The new generation of radar has to be equipped with a high performance exciters and receivers to cope with the threat in an Electronic Warfare scenario. The threat in a complex environment with interfering signals requires a reliable signal generation with proper frequency agility and efficient gain controls in receiver units. This is quite cumbersome to achieve in analog domain. Due to digital technology advancements, it is possible to have efficient and high performance Analog-to-Digital converters (ADC),processors, high-density memories and efficient algorithms to realize highly reliable, flexible and upgradeable exciters and receivers. In this design, exciter unit comprises of various digital modules for waveform generation, clocks and synchronization signal generation for different sub-systems of the radar and digital code generation for the frequency to be synthesized. These codes are used to control the Local Oscillators (LOs) output utilized for the up-conversion. In the Receiver unit main focus is on the digital implementation of gain control like sensitivity-time-control (STC), Generation of various controls required by Synthetic noise generator and Automatic Gain Control (AGC) and Digital amplitude Phase Demodulation (DAPD) of down-converted sampled intermediate frequency (IF) signals. This work projects the digital design methodology behind the various modules identified for the Radar Signal Generation and Receiver units. The main highlight of the paper is that the entire design models described are implemented using digital methods using FPGAs. The Xilinx System Generator (XSG) design tool is used to accomplish this, which generates directly the code for a Xilinx FPGA on a target board.
新一代雷达必须配备高性能激励器和接收机,以应对电子战场景中的威胁。在具有干扰信号的复杂环境中,威胁需要可靠的信号产生,适当的频率敏捷性和接收机单元的有效增益控制。这在模拟域实现起来相当麻烦。由于数字技术的进步,有可能拥有高效和高性能的模数转换器(ADC),处理器,高密度存储器和高效算法来实现高可靠,灵活和可升级的励磁器和接收器。在本设计中,励磁单元由各种数字模块组成,分别用于雷达各子系统的波形产生、时钟和同步信号的产生以及要合成的频率的数字编码产生。这些代码用于控制用于上转换的本地振荡器(LOs)输出。在接收单元中,主要重点是数字实现增益控制,如灵敏度-时间控制(STC),合成噪声发生器和自动增益控制(AGC)所需的各种控制,以及下变频采样中频(IF)信号的数字幅度相位解调(DAPD)。这项工作规划了雷达信号产生和接收单元确定的各种模块背后的数字设计方法。本文的主要亮点是所描述的整个设计模型都是使用fpga的数字方法实现的。Xilinx System Generator (XSG)设计工具用于完成此任务,它直接为目标板上的Xilinx FPGA生成代码。