An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Abstract

In this paper we present a tool based approach for an aging-aware design method. Extending the gm/ID sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.