Crosstalk Noise Reduction Techniques Using SOI Substrate

Abstract

As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques using Silicon On Insulator (SOI) substrate. Coupling through common silicon substrate has become an important limiting factor in high performance ICs. A study of the advantages of using SOI substrate in contrast to bulk is presented in this paper. Through MATLAB software, a system of three coupled wires is modeled as RC distributed networks. A resistive model is used to model both SOI and bulk substrates. The results are compared to the bulk in order to show the advantages of using SOI substrate to reduce crosstalk noise in deep sub micron technology.