{"title":"Silt: the bit-parallel approach","authors":"R. Barman, M. Bolotski, D. Camporese, J. Little","doi":"10.1109/ICPR.1990.119378","DOIUrl":null,"url":null,"abstract":"A particular form of parallelism, called bit-parallelism, is introduced. A bit-parallel organization distributes each bit of a data item to a different processor. Bit-parallelism allows computation that is sublinear with word size for such operations as integer addition, arithmetic shifts, and data moves. The implications of bit-parallelism for system architecture are analyzed. An implementation of a bit-parallel architecture based on a mesh with a bypass network is presented. Using a conservative estimate for cycle time, a Silt processor performs 64-b integer additions more than 10 times faster than the Connection Machine-2. Using current CMOS technology, a 16 M processor Silt system would be capable of nearly 500 billion 32-b adds per second. The application of the architecture to low-level vision algorithms is discussed.<<ETX>>","PeriodicalId":135937,"journal":{"name":"[1990] Proceedings. 10th International Conference on Pattern Recognition","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings. 10th International Conference on Pattern Recognition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPR.1990.119378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A particular form of parallelism, called bit-parallelism, is introduced. A bit-parallel organization distributes each bit of a data item to a different processor. Bit-parallelism allows computation that is sublinear with word size for such operations as integer addition, arithmetic shifts, and data moves. The implications of bit-parallelism for system architecture are analyzed. An implementation of a bit-parallel architecture based on a mesh with a bypass network is presented. Using a conservative estimate for cycle time, a Silt processor performs 64-b integer additions more than 10 times faster than the Connection Machine-2. Using current CMOS technology, a 16 M processor Silt system would be capable of nearly 500 billion 32-b adds per second. The application of the architecture to low-level vision algorithms is discussed.<>