Modified Positive Feedback Adiabatic Logic for Ultra Low Power Adder

Abstract

This paper proposes a modified positive feedback adiabatic logic (MPFAL) for ultra-low power circuits. MPFAL is based on positive DC voltage range 0.1 to 0.3 V. Half-adder and 1-bit full-adder incorporating this technique also been considered in this work. Comparison shows that average power is reduced in case of modified technique compared to positive feedback adiabatic logic (PFAL) for frequency range 10 MHz to 300 MHz and simulations are carried out by considering load capacitance from 30fF to 110fF. All the simulations have been done in Cadence Virtuoso Tool using UMC 180 nm CMOS technology. This technique can be used in ultra-low power digital circuits operated at higher frequencies.