Instruction-driven timing CPU model for efficient embedded software development using OVP

Abstract

The software complexity of MPSoCs is increasing dramatically, resulting in new design challenges, such as improving the system's performance and programmability by porting parallel programming APIs. Such challenges impose more time and cost on the system's software development. This leads to the adopting of virtual platform frameworks aimed at functional verification like OVP, capable of simulating embedded systems running real application code at the speed of hundreds of MIPS. This work focuses on enhancing OVP capability by including a quasi-cycle accurate timing CPU model, making it suitable for performance analysis. This paper also evaluates the accuracy of the proposed timing CPU model when compared to a real system. Results show that the accuracy of our model varies from 0.06% to 10.56% depending on the benchmark profile.